1. Field of the Invention
Embodiments of the present invention relate to a semiconductor memory device including a flash memory cell array and a mask read-only memory (ROM) cell array and a method of manufacturing the semiconductor memory device.
This application claims the priority of Korean Patent Application No. 2003-44544, filed on Jul. 2, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
System-on-chips (SOCs) integrate essential system functions onto one chip. Since both hardware and software are merged and both analog and digital are integrated in the SOCs, a single semiconductor chip can operate as a system. In other words, SOCs can contain all functions in a single semiconductor chip, such as memory, non-memory (large scale integrated circuit (LSI)), analog components, digital components, hardware, and software. SOCs can be applied to various fields of technology, such as a digital systems included in cellular telephones. SOCs are widely applied to high-density and high-performance products. While processes for devices under 0.13 μm have been primarily used in manufacturing semiconductor devices, applications of the SOCs are expanding. SOCs may include a mask read-only memory (ROM), on which various data is coded. SOCs may include a non-volatile memory (NVM) device, such as an electrically erasable and programmable read-only memory (EEPROM) or a flash memory from which a user can program and erase data.
FIG. 1 is a block diagram illustrating an inner configuration of the semiconductor chip 100, which includes an EEPROM and a mask ROM. The semiconductor chip 100 may be a SOC or a microcomputer chip. The semiconductor chip 100 may include the EEPROM block 110, the mask ROM block 120, and the core block 130. The semiconductor chip 100 may further include a buffer memory (not shown) having a static random access memory (SRAM). The core block 130 may include a controller unit (similar to a central processing unit (CPU)) and a logic integrated circuit (IC) comprising analog circuits and digital circuits.
The EEPROM block 110 includes the EEPROM cell array unit 112 (referred to as an EEPROM unit hereinafter) and the peripheral circuit unit 114. A transistor included in the EEPROM unit 112 may be a stack gate transistor having a gate structure in which a floating gate, an insulating layer, and a control gate are stacked. Alternatively, a transistor included in the EEPROM unit 112 may be a split gate transistor having a split gate structure. The peripheral circuit unit 114 may comprise a circuit necessary for programming and erasing data into and from the EEPROM unit 112. The mask ROM block 120 may include a mask ROM cell array unit 122 (referred to as a mask ROM unit hereinafter) and the peripheral circuit unit 124. A transistor included in the mask ROM unit 122 may be a metal oxide semiconductor (MOS) transistor or a stack gate transistor having a gate structure in which a floating gate, an insulating layer, and a control gate are stacked. The peripheral circuit unit 124 may comprise a circuit necessary for reading information stored in the mask ROM unit 122.
The EEPROM block 110 and the mask ROM block 120 have the peripheral circuit units 114 and 124 formed at their peripheries. A relatively large isolation layer is interposed between the EEPROM block 110 and the mask ROM 120 to separate the two blocks. Cell transistors including the EEPROM unit 112 and the mask ROM unit 122 are different types. In particular, a transistor included in the mask ROM unit 122 has a simple MOS gate structure, which is different from a transistor included in the EEPROM unit 112.
FIG. 2 is a schematic cross-section partially illustrating an EEPROM unit and a mask ROM unit. The semiconductor substrate 200 is separated into an EEPROM cell array region (referred to as an EEPROM region hereinafter) and the mask ROM cell array region (referred to as a mask ROM region hereinafter) by the isolation layer 205. The EEPROM region is occupied by the EEPROM block 110 (see FIG. 1) and the mask ROM region is occupied by the mask ROM block 120 (see FIG. 1). FIG. 2 shows cell transistors of the memory cell array units included in the blocks 110 and 120.
The split gate structure 210 in which the gate oxide layer 211, the floating gate 212, the insulating layers 213a and 213b, and the control gate 215 are stacked and formed in the EEPROM region of the semiconductor substrate 200. The floating gate 212 and the control gate 215 may be made of polysilicon, metal, and/or metal silicide. The insulating layer 213a may be a thermal oxidation layer made of polysilicon. The insulating layer 213b may be an oxide layer deposited through a chemical vapor deposition (CVD) process (or similar process). The source region 242 and the drain region 244 are formed in the semiconductor substrate 200 adjacent to the split gate structure 210.
In the mask ROM region, the gate structure 220 including the gate oxide layer 221 and the gate electrode 222 formed on the semiconductor substrate 200. The gate structure 220 may further include an etch stop layer 225, depending on the manufacturing method. The source region 242 and the drain region 244 are formed in the semiconductor substrate 200 adjacent to the gate structure 210. Data may be coded in some cells of the mask ROM region. For example, a dopant ion-implanted region 230 may be formed on a channel portion of an off cell transistor.
The EEPROM block and the mask ROM block are separated from each other. The two blocks are separated by their peripheral circuits formed in the peripheries of the memory cell array units. Also, the two blocks are electrically separated by the isolation layer formed on the semiconductor substrate. Such structures may be obstacles to improvements in the degree of integration of semiconductor memory devices. Data on specific programs of companies selling SOC-embedded products are usually coded in the mask ROM unit. When the mask ROM block and the EEPROM block are formed separately, there is the possibility of leaking information of the programs.
In manufacturing and selling a mask ROM, several tests are performed. Specifically, after determining if programs are properly executed, based on the coded data being repeatedly tested, final goods are produced. During the test, a process of coding the program data is repeated using an EEPROM or a flash memory, instead of the mask ROM. After the test, if errors do not occur, the program data is coded in a mask ROM form and contained in the SOC. However, a cell transistor including in an EEPROM unit or a flash memory unit is different from the kind included in a mask ROM unit. Even if the mask ROM passed the test, the program data is coded using the mask ROM. The test is then conducted again to ensure reliability on products regardless of difference in the cell transistors. As a result, the repeated testing requires a lot of time to confirm if the mask ROM is correctly executing, to ensure reliability.